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TDA7438
THREE BANDS DIGITALLY CONTROLLED AUDIO PROCESSOR
1
FEATURES
INPUT MULTIPLEXER - 3 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES
Figure 1. Package
SO28
DIP28

ONE STEREO OUTPUT TREBLE, MIDDLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - -INDEPENDENT MUTE FUNCTION
Table 1. Order Codes
Part Number TDA7438 TDA7438D TDA7438D013TR Package DIP28 SO28 Tape & Reel

ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS
Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
2
DESCRIPTION
The TDA7438 is a volume tone (bass, middle and treble) balance (Left/Right) processor for quality audio applications in car-radio and Hi-Fi systems. Figure 2. Block Diagram
MUXOUTL L-IN1 3 100K 4 100K 5 100K G VOLUME 6 INL 7
TREBLE(L) 18
MIN(L) MOUT(L) BIN(L) 17 RM 16 14 RB
BOUT(L) 15
L-IN2
L-IN3
TREBLE
MIDDLE
BASS
SPKR ATT LEFT
27
LOUT
R-IN1
2 100K 1 100K 28
0/30dB 2dB STEP
21 I2CBUS DECODER + LATCHES 22 20
SCL SDA DIG_GND
R-IN2
G
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT RIGHT VREF
26
ROUT
R-IN3
100K 24 INPUT MULTIPLEXER + GAIN 8 MUXOUTR INR 9 19 TREBLE(R) SUPPLY RM 10 11 12 RB 13 23
D96AU488A
25
VS AGND
MIN(R) MOUT(R) BIN(R)
BOUT(R) CREF
June 2004
REV. 7 1/19
TDA7438
Table 2. Absolute Maximum Ratings
Symbol VS Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 0 to 70 -55 to 150 Unit V C C
Figure 3. Pin Connection
R_IN2 R_IN1 L_IN1 L_IN2 L_IN3 MUXOUTL INL MUXOUTR INR MIN(R) MOUT(R) BIN(R) BOUT(R) BIN(L)
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D96AU489A
28 27 26 25 24 23 22 21 20 19 18 17 16 15
R_IN3 LOUT ROUT AGND VS CREF SDA SCL DIG-GND TREBLE(R) TREBLE(L) MIN(L) MOUT(L) BOUT(L)
Table 3. Thermal Data
Symbol Rth j-pins Parameter Thermal Resistance Junction-pins Max. Value 85 Unit C/W
Table 4. Quick Reference Data
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V = 1Vrms f = 1KHz Signal to Noise Ratio Vout = 1Vrms (mode = OFF) Channel Separation f = 1KHz Input Gain in (2db step) Volume Control (1db step) Treble Control (2db step) Middle Control (2db step) Bass Control (2dB step) Balance Control 1dB step Mute Attenuation (*) 0 -47 -14 -14 -14 -79 80 100 Parameter Min. 6 2 0.01 106 90 30 0 +14 +14 +14 0 0.1 Typ. 9 Max. 10.2 Unit V Vrms % dB dB dB dB dB dB dB dB dB
(*) Even applied to Speaker Attenuator Left, Speaker Attenuator Right, Volume Control stand alone or to the combination, if any.
2/19
TDA7438
Table 5. Electrical Characteristcs: (refer to the test circuit Tamb = 25C, VS = 9V, RL= 10K, RG = 600, all controls flat (G = 0dB), unless otherwise specified)
Symbol SUPPLY
VS IS
Parameter
Test Condition
Min.
Typ.
Max.
Unit
Supply Voltage Supply Current Ripple Rejection
6
9 7
10.2
V mA dB
SVR
60
90
INPUT STAGE RIN VCL SIN
Ginmin
Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution THD = 0.3% The selected input is grounded through a 2.2 capacitor 2 80 -1
100 2.5 100 0 30 2 1
K Vrms dB dB dB dB
Ginman Gstep
VOLUME CONTROL
Ri
Input Resistance Control Range Max. Attenuation Step Resolution Attenuation Set Error AV = 0 to -24dB AV = -24 to -47dB
20 45 45 0.5 -1.0 -1.5
33 47 47 1 0 0 0 0 0 0.5
50 49 49 1.5 1.0 1.5 1 2 3
K dB dB dB dB dB dB dB mV mV dB
CRANGE AVMAX ASTEP
EA
ET
Tracking Error
AV = 0 to -24dB AV = -24 to -47dB
VDC A
DC Step Mute Attenuation
adjacent attenuation steps from 0dB to AV max 80
mute
100
BASS CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry) Gb BSTEP RB Control Range Step Resolution Internal Feedback Resistance Max. Boost/cut +12.0 1 33 +14.0 2 44 +16.0 3 55 dB dB K
TREBLE CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry) Gt TSTEP Control Range Step Resolution Max. Boost/cut +13.0 1 +14.0 2 +15.0 3 dB dB
MIDDLE CONTROL (The center frequency and the response quality can be chosen by the ext. circuitry) Gm MSTEP
RM
Control Range Step Resolution Internal Feedback Resistance
Max. Boost/cut
+12.0 1 18.75
+14.0 2 25
+16.0 3 31.25
dB dB K
3/19
TDA7438
Table 5 (continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
SPEAKER ATTENUATORS CRANGE Control Range SSTEP EA Step Resolution Attenuation Set Error AV = 0 to -20dB AV = -20 to -56dB ET Tracking Error AV = 0 to -24dB AV = -24 to -47dB VDC Amute DC Step Mute Attenuation adjacent attenuation steps 80 0.5 -1.5 -2 76 1 0 0 0 0 0 100 1.5 1.5 2 1 2 3 dB dB dB dB dB dB mV dB
AUDIO OUTPUTS VCLIP RL RO VDC Clipping Level Output Load Resistance Output Impedance DC Voltage Level d = 0.3% 2.1 2 10 40 3.8 70 2.6 VRMS K W V
GENERAL (Gain, Bass, Treble, Middle Controls Flat) ENO Et Output Noise Total Tracking Error (Volume + Speaker Attenuator) All gains = 0dB; BW = 20Hz to 20KHz flat AV = 0 to -24dB AV= -24 to -47dB AV = -47 to -79dB S/N SC d Signal to Noise Ratio Channel Separation Left/Right Distortion AV = 0; VI = 1VRMS ; All gains 0dB; VO = 1VRMS ; 90 80 5 0 0 0 106 100 0.01 0.08 15 1 2 3 V dB dB dB dB dB %
BUS INPUT VIL VIH IIN Input Low Voltage Input High Voltage Input Current VIN = 0.4V 3 -5 5 1 V V A
4/19
TDA7438
Figure 4. Test Circuit
5.6nF 2.2F 2.7K 18nF MIN(L) 5.6K 22nF 100nF 100nF
MUXOUTL L-IN1 0.47F L-IN2 0.47F L-IN3 0.47F 5 100K 4 100K G 3 100K 6
INL
TREBLE(L) 7 18
MOUT(L) 17 RM 16
BIN(L) 14 RB
BOUT(L) 15
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT LEFT
27
LOUT
R-IN1 0.47F R-IN2 0.47F R-IN3 0.47F
2 100K 1 100K 28 100K
0/30dB 2dB STEP
21 I CBUS DECODER + LATCHES
2
22 20
SCL SDA DIGGND
G
VOLUME
TREBLE
MIDDLE
BASS
SPKR ATT RIGHT VREF
26
ROUT
24 INPUT MULTIPLEXER + GAIN 8 MUXOUTR INR 9 TREBLE(R) 19 MIN(R) 10 RM 11 12 BIN(R) RB 13 BOUT(R) SUPPLY 25
VS AGND
23 CREF
MOUT(R)
2.2F 5.6nF
18nF 2.7K
22nF 100nF 5.6K
100nF
10F
D96AU490A
3
APPLICATION SUGGESTIONS
The first and the last stages are volume control blocks. The control range is 0 to -47dB (mute) for the first one, 0 to -79dB (mute) for the last one. Both of them have 1dB step resolution. The very high resolution allows the implementation of systems free from any noisy acoustical effect. The TDA7438 audioprocessor provides 3 bands tones control. 3.1 Bass, Middle Stages The Bass and the middle cells have the same structure. The Bass cell has an internal resistor Ri = 44K typical. The Middle cell has an internal resistor Ri = 25K typical. Several filter types can be implemented, connecting external components to the Bass/Middle IN and OUT pins. Figure 5.
Ri internal IN C1 R2
D95AU313
OUT C2
5/19
TDA7438
The fig.5 refers to basic T Type Bandpass Filter starting from the filter component values (R1 internal and R2,C1,C2 external) the centre frequency Fc, the gain Av at max. boost and the filter Q factor are computed as follows:
1 F c = ---------------------------------------------------------2 Ri, R2, C1, C2
R2C2 + R2C1 + RiC1 A V = -----------------------------------------------------------R1C1 + R2C2
Ri, R2, C1, C2 Q = -----------------------------------------R2C1 + R2C2
Viceversa, once Fc, Av, and Ri internal value are fixed, the external components values will be:
AV - 1 C1 = ----------------------------2 Ri Q Q C1 C2 = ----------------------2 A V - 1Q
2
AV - 1 - Q R2 = --------------------------------------------------------------------2 C1 F c ( A V - 1 ) Q
2
3.2 Treble Stage The treble stage is a high pass filter whose time constant is fixed by an internal resistor (25K typical) and an external capacitor connected between treble pins and ground Typical responses are reported in Figg. 14 to 17. 3.3 CREF The suggested 10mF reference capacitor (CREF) value can be reduced to 4.7mF if the application requires faster power ON. Figure 6. THD vs. frequency Figure 7. THD vs. RLOAD
6/19
TDA7438
Figure 8. Channel separation vs. frequency Figure 11. Middle response
Figure 9. Bass response
Figure 12. Typical tone response
Figure 10. Treble response
7/19
TDA7438
4
I2C BUS INTERFACE
Data transmission from microprocessor to the TDA7438 and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). 4.1 Data Validity As shown in fig. 12, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. 4.2 Start and Stop Conditions As shown in fig.13 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. 4.3 Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. 4.4 Acknowledge The master (mP) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 14). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. 4.5 Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the mP can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 13. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 14. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
8/19
TDA7438
Figure 15. Acknowledge on the I2CBUS
SCL
1
2
3
7
8
9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
5
SOFTWARE SPECIFICATION
Interface Protocol The interface protocol comprises:

A start condition (S) A chip address byte, containing the TDA7438 address A subaddress bytes A sequence of data (N byte + acknowledge)
Figure 16.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge S = Start P = Stop A = Address B = Auto Increment
5.1 EXAMPLES 5.1.1 No Incremental Bus The TDA7438 receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition. Figure 17.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
5.1.2 Incremental Bus The TDA7438 receive a start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition
9/19
TDA7438
Figure 18. .
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
Table 6. POWER ON RESET CONDITION
INPUT SELECTION INPUT GAIN VOLUME BASS MIDDLE TREBLE SPEAKER IN2 28dB MUTE 0dB 2dB 2dB MUTE
6
DATA BYTES
Address = 88 HEX (ADDR:OPEN). Table 7. FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X X D6 X X X X X X X X D5 X X X X X X X X D4 B B B B B B B B D3 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB SUBADDRESS D0 0 1 0 1 0 1 0 1 INPUT SELECT INPUT GAIN VOLUME BASS MIDDLE TREBLE SPEAKER ATTENUATE "R" SPEAKER ATTENUATE "L"
B = 1: INCREMENTAL BUS ACTIVE B = 0: NO INCREMENTAL BUS X = DON'T CARE
Figure 19. INPUT SELECTION
MSB D7 X X X X D6 X X X X D5 X X X X D4 X X X X D3 X X X X D2 X X X X D1 0 0 1 1 LSB INPUT MULTIPLEXER D0 0 1 0 1 IN3 NOT ALLOWED IN2 IN1
10/19
TDA7438
Table 8. INPUT GAIN SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
GAIN = 0 to 30dB
LSB D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
INPUT GAIN 2dB STEPS 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB 16dB 18dB 20dB 22dB 24dB 26dB 28dB 30dB
Table 9. VOLUME SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 X
VOLUME = 0 to 47dB/MUTE
LSB D1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1
VOLUME 1dB STEPS 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 0dB -8dB -16dB -24dB -32dB -40dB
0 0 0 0 1 1 1
0 0 1 1 0 0 1
0 1 0 1 0 1 1 X X X
MUTE
11/19
TDA7438
Table 10. BASS SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 BASS 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
Table 11. MIDDLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 MIDDLE 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
12/19
TDA7438
Table 12. TREBLE SELECTION
MSB D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 D1 0 0 1 1 0 0 1 1 1 1 0 0 1 1 0 0 LSB D0 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 TREBLE 2dB STEPS -14dB -12dB -10dB -8dB -6dB -4dB -2dB 0dB 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
Table 13. SPEAKER ATTENUATE SELECTION
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 LSB D0 0 1 0 1 0 1 0 1 SPEAKER ATTENUATION 1dB 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB
0 0 0 0 0 0 0 0 1 1 1
0 0 0 0 1 1 1 1 0 0 1
0 0 1 1 0 0 1 1 0 0 1
0 1 0 1 0 1 0 1 0 1 1 X X X
0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB -64dB -72dB MUTE
SPEAKER ATTENUATION = 0 to -79dB/MUTE
13/19
TDA7438
Figure 20. PINS: 23 Figure 23. PINS: 6, 8
VS
VS 20K
VS
VS 20A
CREF 20K
MUXOUT
GND
D96AU430
D96AU491
Figure 21. PINS: 26, 27
VS
Figure 24. PINS: 7, 9
VS
ROUT LOUT 24
20A
INL INR
20A
33K
D96AU427
VREF
D96AU434
Figure 22. PINS: 1, 2, 3, 4, 5, 28
Figure 25. PINS: 10, 11
VS VS 20A 20A
IN
100K VREF
D96AU425
25K MOUT(L) MOUT(R)
D96AU431
14/19
TDA7438
Figure 26. PINS: 10, 17 Figure 29. PINS: 18, 19
VS VS 20A 20A
25K MOUT(L) MOUT(R)
D96AU431
44K BIN(L) BIN(R)
D96AU428
Figure 27. PINS: 12, 14
VS 20A
Figure 30. PIN: 20
20A SCL
44K BIN(L) BIN(R)
D96AU428
D96AU424
Figure 28. PINS: 13, 15
Figure 31. PINS: 21
VS 20A
20A SDA
44K BOUT(L) BOUT(R)
D96AU429
D96AU423
15/19
TDA7438
Figure 32. DIP28 Mechanical Data & Package Dimensions
mm DIM. MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 33.02 14.1 0.23 1.27 37.34 16.68 0.598 TYP. 0.63 0.45 0.31 0.009 MAX. MIN.
inch TYP. 0.025 0.018 0.012 0.050 1.470 0.657 0.100 1.300 0.555 0.175 MAX.
OUTLINE AND MECHANICAL DATA
DIP28
0.130
16/19
TDA7438
Figure 33. SO28 Mechanical Data & Package Dimensions
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO-28
8 (max.)
17/19
TDA7438
Table 14. Revision History
Date January 2004 June 2004 Revision 6 7 Description of Changes First Issue in EDOCS DMS Changed the Style-sheet in compliance to the new "Corporate Technical Pubblications Design Guide"
18/19
TDA7438
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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